Semiconductor memory device having advanced test mode

ABSTRACT

An apparatus for testing an operation of a semiconductor memory device having a plurality of banks in a compress test mode includes an internal address generator for receiving an external bank address and generating internal bank addresses in response to a bank interleaving test signal; a read operation testing block for receiving the internal bank addresses and testing a read operation of the semiconductor memory device in response to the bank interleaving test signal; and a write operation testing block for receiving the internal bank addresses and testing a write operation of the semiconductor memory device.

The present patent application is a continuation of application Ser. No.10/882,740, filed Jun. 30, 2004 now U.S. Pat. No. 7,321,991.

FIELD OF INVENTION

The present invention relates to a semiconductor memory device; and,more particularly, to a semiconductor memory device having enhanceability of a test for finding fault of an operation of a semiconductormemory device in a bank interleaving mode.

DESCRIPTION OF PRIOR ART

A semiconductor memory device includes a plurality of memory cells. Ifany cell in the semiconductor memory device is operated out of order,the semiconductor memory device is useless. After the semiconductormemory device is fabricated, there is needed a test process for findinga defective cell in the semiconductor memory device.

Typically, the semiconductor memory device has an additional area for atest circuit which can test all cells in the semiconductor memory deviceon high speed. However, according to increasing integration of thesemiconductor memory device, there is needed a lot of time and effortfor testing cells of the semiconductor memory device so as to researchand develop the semiconductor memory device.

Thus, for saving the time to test the semiconductor memory device, acompress test mode is used. In the compress test mode, data issimultaneously inputted to all banks included in the semiconductorthroughout a part of input/output pins DQs, not all of input/outputpins. For checking data outputted from each unit cell, each inputteddata is not simultaneously outputted from all banks throughout all ofinput/output pins DQs and, as a substitute, a plurality of logic gates,e.g., a AND gate or a NOR gate, each for corresponding to eachinput/output pin DQ, are used.

FIG. 1 is a block diagram showing a test block used in a conventionalsemiconductor memory device.

As shown, the test block includes an internal bank address generator 10,a read decoding block 20, a compress controlling block 30, a datacompress block 40, a write decoding block 50, a write controlling block60 and a writing driving block 70.

The internal bank address generator 10 converts a bank address, e.g.,BA0 and BA1, into a plurality of internal bank addresses, i.e., a, /a,b, /b, c, /c, d, /d. The plurality of internal bank addresses, i.e., a,/a, b, /b, c, /c, d, /d, are inputted to the read decoding block 20. Theread decoding block 20 decodes the plurality of internal bank addresses,i.e., a, /a, b, /b, c, /c, d, /d, to thereby generate a plurality ofread bank operating signals rd_bank0, rd_bank1, rd_bank2 and rd_bank3 inresponse to an additive latency signal AL0. The compress controllingblock 30 is for controlling the data compress block 40 in response tothe plurality of read bank operating signals rd_bank0, rd_bank1,rd_bank2 and rd_bank3. The data compress block 40 having a plurality ofDQ output buffers, e.g., 36, is for compressing data outputted from eachbank.

In addition, parts of the plurality of internal bank addresses, i.e., a,/a, b, /b, are inputted to the write decoding block 50. The writedecoding block 50 decodes the parts of plurality of internal bankaddresses, i.e., a, /a, b, /b, to thereby generate a plurality of writebank operating signals wt_bank0, wt_bank1, wt_bank2 and wt_bank3. Thewrite controlling block 60 is for controlling the write driving block 70in response to a write activation signal WTen and the plurality of writebank operating signals wt_bank0, wt_bank1, wt_bank2 and wt_bank3. Thewrite driving block 70 is for storing inputted data to a cell arrays 80included in each bank.

Furthermore, the internal bank address generator 10 includes a bufferblock, a latch block and a routing block. The buffer block includes twobuffers, e.g., 12, each for receiving a first bit bank address BA0 and asecond bit bank address BA1 and converting the first bit bank addressBA0 and the second bit bank address BA1 into an internal bank address,i.e., ba0_add, ba0_addb, ba1_add and ba1_addb, each corresponding to thefirst bit bank address BA0 and the second bit bank address BA1. Thelatch block includes two latches, e.g., 14, each controlled by acompress test signal tpara for transmitting the internal bank address,i.e., ba0_add, ba0_addb, ba1_add and ba1_addb, to the routing block asthe parts of the plurality of internal bank addresses, i.e., a, /a, b,/b. The routing block also includes two routers, e.g., 16, each fordelaying the parts of the plurality of internal bank addresses, i.e., a,/a, b, /b, to thereby generate others of the plurality of internal bankaddresses, i.e., c, /c, d, /d.

In detail, the compress controlling block 30 includes a read controllingblock 32 and a strobe signal generating block 34. The read controllingblock 32 includes a plurality of read controllers, each controlled by aread activation signal RDen for receiving the read bank operatingsignal; and the strobe signal generating block 34 includes a pluralityof strobe signal generators, each for generating a plurality of strobesignals, e.g., iostb.

Herein, each read controller, each strobe signal generator and each DQoutput buffer are respectively corresponded to each bank included in theconventional semiconductor memory device. In addition, each buffer, eachlatch and each router in the internal bank address generator 10 arerespectively corresponded to each bit of the bank address.

Hereinafter, there is described a test operation of the conventionalsemiconductor memory device when the compress test signal tpara isactivated.

First, the internal bank address generator 10 activates the plurality ofinternal bank addresses, i.e., a, /a, b, /b, c, /c, d, /d, in responseto the compress test signal tpara without a regard of the bank address.Then, the plurality of read bank operating signals rd_bank0, rd_bank1,rd_bank2 and rd_bank3 outputted from the read decoding block 20 and theplurality of write bank operating signals wt_bank0, wt_bank1, wt_bank2and wt_bank3 outputted from the write decoding block 50 are activated.If the write activation signal WTen is activated, the write controllingblock 60 and the writing driving block 70 are activated and, then, dataare inputted to the cell arrays 80. Otherwise, if the read activationsignal RDen is activated, a plurality of data LI00<0:15> to LI03<0:15>outputted from the cell arrays 80 is compressed and outputted.

Furthermore, an operation of the test block, i.e., methods for decodingcompressed data and compressing outputted data, are described in detail.

In the conventional memory device, each bank has one data pad forreceiving four data once. The four data is considered as one data bunch;and four data bunches constitute a 16-bit data. At a write operation,the same 16-bit data is inputted to each bank.

At a read operation, the 16-bit data inputted to each bank is classifiedinto four data bunch; and each datum, which is inputted throughout thesame data pad, among four data of each data bunch is compared with eachother. Then, through the data pad corresponding to each bank, thecomparison result is outputted.

Herein, if a logic state of signal outputted throughout the data pad isa logic high level, the semiconductor memory device has no defectivecell; but, otherwise, the semiconductor memory device has at least onedefective cell.

FIG. 2 is a schematic circuit diagram describing the latch included inthe latching block 14 shown in FIG. 1.

As shown, the latch includes a first inverter I1, first latch unit 14 a,a second latch unit 14 b, a first NAND gate ND1 and a second NAND gateND2. Herein, the first and second latch units 14 a and 14 b areconstituted with two circularly connected inverters.

The first inverter I1 is for inverting the compress test signal tpara.The first latch unit 14 a is for latching an inverse internal bankaddress, e.g., ba0_addb; and the second latch unit 14 b is for latchingan internal bank address, e.g., ba0_add. The first NAND gate ND1 coupledto the first latch unit 14 a and the first inverter I1 receives aninverse state of the inverse internal bank address, i.e., internal bankaddress, and an inverse compress test signal to generate a result signalof the NAND operation as a first internal bank address a. Also, thesecond NAND gate ND2 coupled to the second latch unit 14 b and the firstinverter I1 receives an inverse state of the internal bank address,i.e., inverse internal bank address, and an inverse compress test signalto generate a result signal of the NAND operation as a first barinternal bank address /a.

FIG. 3 is a schematic circuit diagram describing the router included inthe routing block 14 shown in FIG. 1.

As shown, the router includes a latching and delaying block 17, a secondinverter I2, a third NAND gate ND3 and a fourth NAND gate ND4.

The latching and delaying block 17 receives the first internal bankaddress, i.e., a, and the first bar internal bank address, i.e., /a,outputted from the latch to thereby output a delay signal to the thirdNAND gate. The second inverter I2 is for inverting the compress testsignal tpara. The third NAND gate ND3 coupled to the latching anddelaying block 17 and the second inverter I2 receives an outputtedsignal from the latching and delaying block 17 and an inverse compresstest signal to generate a result signal of the NAND operation as a thirdinternal bank address c. Also, the second NAND gate ND2 coupled to thefirst inverter I1 receives the third internal bank address, i.e., c, andan inverse compress test signal to generate a result signal of the NANDoperation as a third bar internal bank address /c.

With a reference, each latch and each router respectively have the samestructures; and, thus, detailed descriptions of other latches androuters are omitted.

FIG. 4 is a schematic circuit diagram describing the read decoding block20 shown in FIG. 1.

As shown, the read decoding block 20 includes a control signal generator21 and a plurality of decoders 22, 24, 26 and 28. The control signalgenerator 21 is for generating control signals, e.g., AL0 b and AL0 d,in response to the additive latency signal AL0. Each decoder receivestwo internal bank addresses and selects one of the two internal bankaddresses in response to the control signals, e.g., AL0 b and AL0 d, tothereby generate an inverse selected address as the read bank operationsignal.

In detail, the control signal generator 21 includes a third inverter I3for inverting the compress test signal tpara, a fifth NAND gate ND5 forgenerating a result signal of the NAND operation of the additive latencysignal AL0 and the inverse compress test signal and a fourth inverter I4for inverting a first control signal AL0 b, i.e., an outputted signalfrom the fifth NAND gate ND5, to thereby generate a second controlsignal AL0 d.

Each decoder includes two NAND gates, two transfer gates and oneinverter. Each of the two NAND gates receives two internal bankaddresses and generates a result signal of the NAND operation; each ofthe two transfer gates transmits the result signal in response to thefirst and second control signals AL0 b and AL0 d. Then, the inverter isfor converting output signals from the two transfer gates to therebygenerate an inverse signal of the output signals as the read bankoperating signal.

Referring to FIG. 4, there are four decoders included in the readingdecoding block 20. The plurality of internal bank addresses, i.e., a,/a, b, /b, c, /c, d, /d, are classified into four groups, each includingfour internal bank addresses: (/a, /b, /c, /d), (a, /b, c, /d), (/a, b,/c, d) and (a, b, c, d).

Herein, each decoder, e.g., 22, 24, 26 and 28, decodes one group ofnon-delay internal bank addresses, i.e., a, /a, b, /b, which areoutputted from the latch block, and delay internal bank addresses, i.e.,c, /c, d, /d, which are outputted from the routing block in response tothe first and second control signals AL0 b and AL0 d.

In the conventional memory device, it is required a RAS to CAS delaytRCD which is the minimum time from supplying a row activation signal tosupplying a column activation signal. However, as an additive latency isintroduced for increasing an operation speed of the semiconductor memorydevice, the column activation signal is supplied before the RAS to CASdelay tRCD after the row activation signal is supplied. That is,according to the additive latency, a timing of supplying the columnactivation signal can be adjusted.

If the additive latency signal AL0 is inactivated, e.g., the additivelatency is 2 or 3, the column activation signal is inputted before theRAS to CAS delay tRCD and, then, there is a lot of time margin foraccessing data in response to the column activation signal. In thiscase, because of a lot of time margin, the delay internal bankaddresses, i.e., c, /c, d, /d, which are delayed by the routing block 16are decoded in the read decoding block 20.

Otherwise, if the additive latency signal AL0 is activated, e.g., theadditive latency is 0, the column activation signal is inputted afterthe RAS to CAS delay tRCD and, then, there is little time margin foraccessing data in response to the column activation signal. In thiscase, because of little time margin, the non-delay internal bankaddresses, i.e., a, /a, b, /b, are decoded in the read decoding block20.

FIG. 5 is a schematic circuit diagram describing the DQ output bufferincluded in the data compress block 40 shown in FIG. 1.

As shown, the DQ output buffer included in data compress block 40includes a strobe control generator 42, a comparison block 44 and astrobe driving block 46. Furthermore, there is shown a GIO driverincluding two MOS transistors PM1 and NM1 serially coupled between asupply voltage and a ground.

The strobe control generator 42 receives the compress test signal tparaand the strobe signal iostb outputted from the strobe signal generatorincluded in signal generating block 34 to thereby generate a first and asecond data strobe signals iostb2 and iostb2 b. The comparison block 44receives each of data LI00<0:15> to LI03<0:15> outputted from the cellarrays 80 in order to compress the 16-bit data. Lastly, the strobedriving block 46 outputs a compressed data outputted from the comparisonblock 44 to the GIO driver in response to the first and the second datastrobe signals iostb2 and iostb2 b.

As above described, the conventional semiconductor memory device cantest all of unit cells so fast by using the compress test mode.

However, the test mode included in the conventional semiconductor memorydevice cannot test a bank interleaving mode because all banks includedin the conventional memory device are simultaneously activated. In fact,the conventional semiconductor memory device operates in the bankinterleaving mode in order to increasing an operation speed. In the bankinterleaving mode, a data collision or a skew can be occurred when datais randomly read or written between each bank.

Therefore, for testing an operation of the conventional semiconductormemory device in the bank interleaving mode, data cannot be compressedand, as a result, a required time for testing is too long.

SUMMARY OF INVENTION

It is, therefore, an object of the present invention to provide asemiconductor memory device having advanced ability for finding fault ofan operation of a semiconductor memory device in a bank interleavingmode in order to reduce a test time.

In accordance with an aspect of the present invention, there is provideda method for testing an operation of a semiconductor memory devicehaving a plurality of banks in a compress test mode including the stepsof: (A) testing the semiconductor memory device by simultaneouslyactivating the plurality of banks; and (B) testing the semiconductormemory device by randomly activating the plurality of banks.

In accordance with another aspect of the present invention, there isprovided an apparatus for testing an operation of a semiconductor memorydevice having a plurality of banks in a compress test mode including aninternal address generator for receiving an external bank address andgenerating internal bank addresses in response to a bank interleavingtest signal; a read operation testing block for receiving the internalbank addresses and testing a read operation of the semiconductor memorydevice in response to the bank interleaving test signal; and a writeoperation testing block for receiving the internal bank addresses andtesting a write operation of the semiconductor memory device.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects and features of the present invention willbecome apparent from the following description of preferred embodimentstaken in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram showing a test block used in a conventionalsemiconductor memory device;

FIG. 2 is a schematic circuit diagram describing a latch included in alatching block shown in FIG. 1;

FIG. 3 is a schematic circuit diagram describing a router included in arouting block shown in FIG. 1;

FIG. 4 is a schematic circuit diagram describing a read decoding blockshown in FIG. 1;

FIG. 5 is a schematic circuit diagram describing a DQ output bufferincluded in a data compress block shown in FIG. 1;

FIG. 6 is a block diagram showing a test block used in a semiconductormemory device in accordance with the present invention;

FIG. 7 is a schematic circuit diagram describing a latch included in alatching block shown in FIG. 6;

FIG. 8 is a schematic circuit diagram describing the router included ina routing block shown in FIG. 6;

FIG. 9 is a schematic circuit diagram describing a DQ output bufferincluded in a data compress block shown in FIG. 1; and

FIG. 10 is a schematic circuit diagram showing a write decoding blockshown in FIG. 6.

DETAILED DESCRIPTION OF INVENTION

Hereinafter, a semiconductor memory device in accordance with thepresent invention will be described in detail referring to theaccompanying drawings.

FIG. 6 is a block diagram showing a test block used in a semiconductormemory device in accordance with the present invention.

As shown, the test block includes an internal address generator 100, aread operation testing block and a write operation testing block.

The internal address generator 100 receives an external bank address,e.g., BA0, and generates internal bank addresses, e.g., a and /a, inresponse to a bank interleaving test signal iocomp. The read operationtesting block is for receiving the internal bank addresses, e.g., a and/a, and testing a read operation of the semiconductor memory device inresponse to the bank interleaving test signal iocomp. The writeoperation testing block receives the internal bank addresses, e.g., aand /a, and tests a write operation of the semiconductor memory device.

Herein, the read operation testing block includes a read decoding block200, a compress controlling block 300 and a data compress block 400; andthe write operation testing block includes a write decoding block 500, awrite controlling block 600 and a writing driving block 700.

In detail, the internal bank address generator 100 converts a bankaddress, e.g., BA0 and BA1, into a plurality of internal bank addresses,i.e., a, /a, b, /b, c, /c, d, /d, in response to a compress test signaltpara and the bank interleaving test signal iocomp. Herein, the internalbank addresses, i.e., a, /a, b, /b, c, /c, d, /d, are classified intonon-delay internal bank addresses, i.e., a, /a, b, /b, and delayinternal bank addresses, i.e., c, /c, d, /d. The plurality of internalbank addresses, i.e., a, /a, b, /b, c, /c, d, /d, are inputted to theread decoding block 200. The read decoding block 200 decodes theplurality of internal bank addresses, i.e., a, /a, b, /b, c, /c, d, /d,to thereby generate a plurality of read bank operating signals rd_bank0,rd_bank1, rd_bank2 and rd_bank3 in response to an additive latencysignal AL0 and the bank interleaving test signal iocomp. The compresscontrolling block 300 is for controlling the data compress block 400 inresponse to the plurality of read bank operating signals rd_bank0,rd_bank1, rd_bank2 and rd_bank3. The data compress block 400 having aplurality of DQ output buffers is for compressing data outputted fromeach bank to thereby output a test result signal in response to thecompress test signal tpara and a bank inactivation signal, e.g.,Xedb_ba.

In addition, the non-delay internal bank addresses, i.e., a, /a, b, /b,are inputted to the write decoding block 500. The write decoding block500 decodes the parts of plurality of internal bank addresses, i.e., a,/a, b, /b, to thereby generate a plurality of write bank operatingsignals wt_bank0, wt_bank1, wt_bank2 and wt_bank3. The write controllingblock 600 is for controlling the write driving block 700 in response toa write activation signal WTen and the plurality of write bank operatingsignals wt_bank0, wt_bank1, wt_bank2 and wt_bank3. The write drivingblock 700 is for storing inputted data to a cell arrays 800 included ineach bank.

Furthermore, the internal bank address generator 100 includes a latchcontroller 180, a buffer block, a latch block and a routing block. Thelatch controller 180 is for receiving the compress test signal tpara andthe bank interleaving test signal iocomp and controlling a latch controlsignal. The buffer block includes two buffers, e.g., 120, each forreceiving a first bit bank address BA0 and a second bit bank address BA1and converting the first bit bank address BA0 and the second bit bankaddress BA1 into an internal addresses, i.e., ba0_add, ba0_addb, ba1_addand ba1_addb, each corresponding to the first bit bank address BA0 andthe second bit bank address BA1. The latch block includes two latches,e.g., 140, each controlled by the latch control signal for transmittingthe internal addresses, i.e., ba0_add, ba0_addb, ba1_add and ba1_addb,to the routing block as the non-delay internal bank addresses, i.e., a,/a, b, /b. The routing block also includes two routers, e.g., 160, eachfor delaying the parts of the plurality of internal bank addresses,i.e., a, /a, b, /b, to thereby generate as the delay internal bankaddresses, i.e., c, /c, d, /d.

In detail, the compress controlling block 300 includes a readcontrolling block 320 and a strobe signal generating block 340. The readcontrolling block 320 includes a plurality of read controllers, eachcontrolled by a read activation signal RDen for receiving the read bankoperating signal and outputting the bank inactivation signal, e.g.,Xedb_ba to the data compress block 400; and the strobe signal generatingblock 340 includes a plurality of strobe signal generators, each forgenerating a plurality of strobe signals, e.g., iostb.

Herein, each read controller, each strobe signal generator and each DQoutput buffer are respectively corresponded to each bank included in theconventional semiconductor memory device. In addition, each buffer, eachlatch and each router in the internal bank address generator 100 arerespectively corresponded to each bit of the bank address.

Hereinafter, there is described a test operation of the semiconductormemory device when the compress test signal tpara is activated.

First, the internal bank address generator 100 activates the pluralityof internal bank addresses, i.e., a, /a, b, /b, c, /c, d, /d, inresponse to the compress test signal tpara and the bank interleavingtest signal iocomp without a regard of the bank address. Then, theplurality of read bank operating signals rd_bank0, rd_bank1, rd_bank2and rd_bank3 outputted from the read decoding block 200 and theplurality of write bank operating signals wt_bank0, wt_bank1, wt_bank2and wt_bank3 outputted from the write decoding block 500 are activated.If the write activation signal WTen is activated, the write controllingblock 600 and the writing driving block 700 are activated and, then,data are inputted to the cell arrays 800. Otherwise, if the readactivation signal RDen is activated in response to the additive latencysignal AL0 and the bank interleaving test signal iocomp, a plurality ofdata LI00<0:15> to LI03<0:15> outputted from the cell arrays 800included in selected bank is compressed and the test result signal isoutputted. At this time, other banks, i.e., not selected banks, outputsa logic high level signal instead of the test result signal in responseto the bank inactivation signal, e.g., Xedb_ba.

Herein, if a logic state of signal outputted throughout the data pad isa logic high level, the semiconductor memory device has no defectivecell; but, otherwise, the semiconductor memory device has at least onedefective cell.

FIG. 7 is a schematic circuit diagram describing the latch 140 and thelatch controller 180 included in a latching block shown in FIG. 6.

As shown, the latch controller 180 includes a fifth inverter I5 and asixth NAND gate ND6; and the latch 140 includes a first latch unit 142,a second latch unit 144, a first NAND gate ND1 and a second NAND gateND2. Herein, the first and second latch units 142 and 144 areconstituted with two circularly connected inverters.

In the latch controller 180, the fifth inverter I5 is for inverting thebank interleaving test signal iocomp. The sixth NAND gate receives anoutput signal from the fifth inverter I5 and the compress test signaltpara to thereby generate a result signal of the NAND operation.

The first latch unit 142 is for latching an inverse internal bankaddress, e.g., ba0_addb; and the second latch unit 144 is for latchingan internal bank address, e.g., ba0_add. The first NAND gate ND1receives an output signal from the latch controller 180 and an inversestate of the inverse internal bank address, i.e., the internal bankaddress, and an inverse compress test signal to generate a result signalof the NAND operation as a first internal bank address a. Also, thesecond NAND gate ND2 receives the output signal from the latchcontroller 180 and an inverse compress test signal to generate a resultsignal of the NAND operation as a first bar internal bank address /a.

FIG. 8 is a schematic circuit diagram describing the router included ina routing block shown in FIG. 6.

As shown, the read decoding block 200 includes a control signalgenerator 210 and a plurality of decoders 220, 240, 260 and 280. Thecontrol signal generator 21 is for generating first and second controlsignals, e.g., AL0 b and AL0 d, in response to the additive latencysignal AL0, the compress test signal tpara and the bank interleavingtest signal iocomp.

Each decoder receives two internal bank addresses and selects one of thetwo internal bank addresses in response to the first and second controlsignals, e.g., AL0 b and AL0 d, to thereby generate an inverse selectedaddress as the read bank operation signal. Herein, each decoder is thesame to each conventional decoder shown in FIG. 4 in their structuresand, thus, detailed operation about each decoder is omitted.

In detail, the control signal generator 210 includes a first NOR gateNR1 for performing the NOR operation of the compress test signal tparaand the bank interleaving test signal iocomp, a ninth NAND gate ND9 forgenerating a result signal of the NAND operation of the additive latencysignal AL0 and an output signal of the first NOR gate NR1 and a sixthinverter I6 for inverting a first control signal AL0 b, i.e., anoutputted signal from the ninth NAND gate ND9, to thereby generate asecond control signal AL0 d.

FIG. 9 is a schematic circuit diagram describing the DQ output bufferincluded in the data compress block 400 shown in FIG. 1.

As shown, the DQ output buffer, e.g., 360, included in data compressblock 400 includes a strobe control generator 420, a comparison block440, a strobe driving block 460 and an output controller 480.Furthermore, there is shown a GIO driver including two MOS transistorsPM2 and NM2 serially coupled between a supply voltage and a ground.

The strobe control generator 420 receives the compress test signal tparaand the bank inactivation signal Xedb_ba and the strobe signal iostboutputted from the strobe signal generator included in signal generatingblock 340 to thereby generate an output control signal tgiob, a firstand a second data strobe signals iostb2 and iostb2 b. The comparisonblock 440 receives each of data LI00<0:15> to LI03<0:15> outputted fromthe cell arrays 80 in order to compress the 16-bit data as the testresult signal. Also, the strobe driving block 460 outputs a compresseddata outputted from the comparison block 440 to the GIO driver inresponse to the first and the second data strobe signals iostb2 andiostb2 b. Lastly, the output controller 480 includes two NAND gates forselectively outputting one of the test result signal and a logic highlevel signal in response to the output control signal tgiob.

Herein, if the bank inactivation signal, e.g., Xedb_ba, is activated,the corresponding bank should output a logic high level signal. It isbecause a bank outputs a logic low level signal if the bank has at leastone defective cell. If one of non-selected banks outputs a logic lowlevel signal, it is impossible to find out a fault in the selected bank.

FIG. 10 is a schematic circuit diagram showing the write decoding block500 shown in FIG. 6.

As shown, the write decoding block 500 includes four NAND gates, eachfor receiving non-delay internal bank addresses to thereby generate thewrite bank operating signal, e.g., wt_bank0. Herein, the write decodingblock 500 receives only non-delay internal bank addresses because alatency for the write operation is generally shorter one clock cyclethan that for the read operation of the semiconductor memory device.

As above described, the test block can test a bank interleaving mode ofthe semiconductor memory device by using the compress test mode. Inaddition, the semiconductor memory device can test all of unit cells sofast by using the compress test mode.

Herein, though the test uses internal bank addresses controlled by theadditive latency in the present invention, the test can be performedwithout a regard of the additive latency.

Therefore, for testing an operation of the semiconductor memory devicein the bank interleaving mode, the compress test mode can be carried outand, as a result, a required time for testing is dramatically reduced.

The present application contains subject matter related to Korean patentapplications No. 2004-18919 and No. 2004-01824, respectively filed inthe Korean Patent Office on Mar. 19, 2004 and on Jan. 10, 2004, theentire contents of which being incorporated herein by references.

While the present invention has been described with respect to theparticular embodiments, it will be apparent to those skilled in the artthat various changes and modifications may be made without departingfrom the spirit and scope of the invention as defined in the followingclaims.

1. A method for testing an operation of a semiconductor memory devicehaving a plurality of banks in a compress test mode, the methodcomprising the steps of: testing the semiconductor memory device bysimultaneously activating the plurality of banks; testing thesemiconductor memory device by selectively activating the plurality ofbanks; and delaying a bank address, which is used for activating eachbank, in order to test an operation of a semiconductor memory devicebased on an additive latency, wherein, in the compress test mode, one ofthe testing steps is selected by a bank interleaving test signal.
 2. Themethod as recited in claim 1, wherein each bank includes one data padfor inputting and outputting data.
 3. The method as recited in claim 2,wherein the step of testing the semiconductor memory device byselectively activating the plurality of banks includes the step ofsupplying normal state information to data pads, each corresponding toeach of inactivated banks except for activated bank, for preventing theinactivated banks from being considered as a defective bank.
 4. A methodfor testing an operation of a semiconductor memory device having aplurality of banks in a compress test mode, the method comprising thesteps of: receiving an external bank address and generating internalbank addresses based on the external bank address in response to acompress test signal and a bank interleaving test signal; receiving theinternal bank addresses and testing a read operation of at least onebank selected by the internal bank addresses in response to an additivelatency signal, the compress test signal and the bank interleaving testsignal; and receiving the internal bank addresses and testing a writeoperation of the selected banks, wherein, in the compress test mode, theplurality of banks are simultaneously activated or selectively activatedin response to the bank interleaving test signal.
 5. The method asrecited in claim 4, wherein the internal bank addresses are classifiedinto non-delay internal bank addresses and delay internal bankaddresses.
 6. The method as recited in claim 5, wherein the step ofreceiving an external bank address and generating internal bankaddresses includes the steps of: receiving the compress test signal andthe bank interleaving test signal and controlling a latch controlsignal; converting the external bank address into the internal bankaddresses; latching the internal addresses to thereby output theinternal addresses as the non-delay internal bank addresses; anddelaying the non-delay internal bank addresses to thereby generate thedelay internal bank addresses.
 7. The method as recited in claim 5,wherein the step of receiving the internal bank addresses and testing aread operation of at least one bank includes the steps of: decoding oneof the non-delay internal bank addresses and the delay internal bankaddresses based on the additive latency signal, the compress test signaland the bank interleaving test signal to thereby generate a plurality ofread bank operating signals; receiving the plurality of read bankoperation signals and generating a plurality of strobe signals; andcompressing a plurality of data outputted from cell arrays in theselected banks and generating a test result signal in response to thecompress test signal and the plurality of strobe signals.
 8. The methodas recited in claim 5, wherein the step of receiving the internal bankaddresses and testing a write operation of the selected banks includesthe steps of: decoding the non-delay internal bank addresses to therebygenerate a plurality of write bank operating signals; receiving theplurality of write bank operating signals and generating a plurality ofwrite driving signals; and storing inputted data in cell arrays in theselected banks in response to the plurality of write driving signals.